Conventionally, there is known an interposer for mounting an electronic component (e.g., MEMS (Micro Electro-Mechanical System) device, a semiconductor device) thereon or an electronic component package including the electronic component mounted on the interposer. For example, an interposer may have a structure formed by layering a silicon substrate including a through-electrode on a frame-like silicon substrate and mounting an electronic component on an inner side of the frame-like silicon substrate (see, for example, Japanese Laid-Open Patent Publication Nos. 2009-4507, 2009-260049).
In recent years, the pitch of wiring patterns (e.g., connection pads) of an electronic component that is mounted on an interposer is becoming narrower. Therefore, the interposer is desired to have a structure corresponding to the narrow pitch of the wiring patterns of the electronic component. The interposer includes a silicon substrate provided with through-electrodes and is structured to mount the electronic component directly on the through-electrodes of the silicon substrate. However, because the interposer is structured to directly mount the electronic component on the through-electrodes, it is difficult to mount an electronic component having narrow-pitched wiring patterns on the through-electrodes.
In order to miniaturize wiring patterns (reduce the pitch of wiring patterns) provided on a side for mounting an electronic component thereon, there is proposed an interposer including multi-layered wiring layers (see, for example, Japanese Laid-Open Patent Publication No. 2009-110983). This interposer includes a silicon substrate having two different layered structures in which one is provided on an upper side of the silicon substrate and the other is provided on a lower side of the silicon substrate.
However, with the interposer having different layered structures provided on the upper and lower sides of the silicon substrate, warping of the interposer occurs.